And then , aiming at the deficiency of conventional design , the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time 其次針對(duì)以往設(shè)計(jì)的不足,采用了以高度集成的fpga (現(xiàn)場(chǎng)可編程邏輯陣列)芯片為核心的設(shè)計(jì)方式,實(shí)現(xiàn)六路光電編碼器信號(hào)的同步實(shí)時(shí)處理。
2 . by analyzing the partial discharge signals and the interferences and using high - speed filed programmable gate array ( fpga ) and digital signal processor ( dsp ) , a hardware and print circuit board have been designed 3 2 )通過(guò)對(duì)局部放電和干擾的分析,針對(duì)局部放電信號(hào)實(shí)時(shí)處理的要求,利用高速的現(xiàn)場(chǎng)可編程邏輯器件和數(shù)字信號(hào)處理器完成了信號(hào)處理的硬件電路板的設(shè)計(jì)與制作。
Because period narrow band signals are the main part of background noises , this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises 3 )在現(xiàn)場(chǎng)環(huán)境中,背景干擾主要是周期性的窄帶,本文利用硬件描述語(yǔ)言( vhdl )設(shè)計(jì)了一個(gè)多帶fir有限沖擊響應(yīng)濾波器。應(yīng)用到可編程邏輯器件中,消除了背景噪聲中的周期性干擾,為信號(hào)的進(jìn)一步處理提供盡可能干凈的信號(hào)。